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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
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<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\crc32_d8.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\ip_checksum.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\gowin_pll\gowin_pll.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\eth_daq_main.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\gmii_rgmii_gmii\gmii_to_rgmii.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\gmii_rgmii_gmii\rgmii_to_gmii.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\eth_data_buf\eth_data_buf.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\eth_msg_buf\eth_msg_buf.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\eth_rx_gmii.v<br>
E:\Workspace\00_Practice\01_FPGA_Workspace\EthernetDAQ_Workspace\fpgaDAQ_project\src\eth_tx_gmii.v<br>
</td>
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<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25UG324C2/I1</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>B</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon Dec 16 17:11:20 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>eth_daq_main</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.232s, Peak memory usage = 740.023MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 740.023MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 740.023MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 740.023MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.295s, Elapsed time = 0h 0m 0.293s, Peak memory usage = 740.023MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>14</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>7</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>7</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspODDR</td>
<td>6</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>0(0 LUT, 0 ALU) / 23040</td>
<td>0%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 23685</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 23685</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 23685</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 56</td>
<td>0%</td>
</tr>
</table>
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